Single Event Upsets(单一事件的不安)研究综述
Single Event Upsets 单一事件的不安 - The distribution of single-event upsets (SEUs) in commercial off-the-shelf (COTS) static random access memory (SRAM) has generally been thought to be uniform in a device. [1] These systems are susceptible to single-event upsets (SEUs) that can corrupt both the hardware configuration and software implementation. [2] Single-event upsets are observed in a 72-layer 3-D NAND flash memory operated in a single-level cell mode after low-energy proton (500 keV–1. [3] Negative and positive muon-induced single-event upsets (SEUs) are studied in 20-nm bulk planar SRAMs. [4] Characterizing low-energy neutrons (<10 MeV)-induced single-event upsets (SEUs) and multiple cells upsets (MCUs) is essential to validate the current standard for terrestrial soft error rate (SER) and investigate its enhancement. [5] This contributes to an increased probability of higher magnitude Single-Event Upsets (SEUs) occurrence in space applications. [6] Mitigation of radiation-induced single-event upsets (SEUs) in the FPGAs is performed by a combination of the Xilinx soft error mitigation (SEM) controller and triple-mode redundancy (TMR) schemes in the FPGA firmware. [7] The impact of heavy ion energy and species on single-event upsets (SEU) sensitivity in state-of-the-art NAND Flash memories is investigated in this paper. [8] However, FPGA based digital channelizers will suffer single-event upsets (SEUs) on the space platform. [9] An SRAM-based FPGA implementation of such a filter is susceptible to memory bit flips that are caused by single-event upsets (SEUs). [10] For this purpose, focusing on basic digital elements, that is, inverters and static random access memories (SRAMs), this study collected more than 100 sets of data on four characteristic parameters of single-event upsets (SEUs) and single-event transients (SETs), both of which are undesired flips in digital logic states. [11] The memories were tested with a reduced refresh rate to expose more single-event upsets and under similar conditions provided by a board specifically developed for this type of study in test facilities. [12] However, FPGAs have been proven to be susceptible to radiation-induced single-event upsets (SEUs). [13] space platform, the memories in the hardware polar decoder will suffer single-event upsets (SEUs) that can cause failures and disrupt communications. [14] When the RS-EC decoder is implemented on a field-programmable gate array (FPGA) in a space platform, it will suffer single-event upsets (SEUs) that can cause failures. [15] As a result, when these deep submicron devices are used in memory cells in the space environment, single-event upsets (SEUs), also known as soft-errors, pose a great threat to the reliability of the cells. [16] The influence of ion track characteristics on single-event upsets (SEU) and multiple-cell upsets (MCUs) is investigated in 65-nm static randon access memory (SRAM) above the heavy-ion linear energy transfer (LET) threshold. [17] However, as a continually shrink of the technology feature sizes, single-event effects (SEEs) such as single-event transients (SETs) and single-event upsets (SEUs) can significantly cause performance degradation of the data converters exposed to radiation environments. [18] This paper presents techniques to assess the effects of soft errors by single-event upsets (SEUs) with formal precision and to relate the results of the proposed analysis to an abstract system model. [19] The uninterrupted operation is possible because of several hardening techniques that allow the SBC to correct single-event upsets (SEUs) in the constituent components. [20] However, the write operation of the SOT-MRAM is more vulnerable to single-event upsets (SEUs) as its ultra-short write pulse is comparable to the radiation current pulse. [21] Furthermore, an analysis was made on single-event upsets and multibit upsets. [22] In order to evaluate the impact of Single-Event Transients in clock distribution networks, the obtained functional failure rate is compared to the error rate caused by Single-Event Upsets in the sequential logic. [23] Compared with previous works, the proposed NVRH-LUT is fully robust against single-event upsets and also single-event double-node upsets that are among the main reliability-challenging issues for NV-LUTs. [24] Cosmic radiation phenomena such as Solar Particle Events cause high radiation flux lasting from hours to days, thus increasing the probability of Single-Event Upsets (SEUs) for several orders of magnitude. [25] The more common types of errors are single-event upsets (SEU) and multiple-bit upset (MBU). [26] Triple modular redundancy (TMR) with repair has proven to be an effective strategy for mitigating the effects of single-event upsets within the configuration memory of static random access memory field-programmable gate arrays. [27] The presented timing generator using mixed-signal delay-locked loop implements the triple combination of the body-feed technique allowing rail-to-rail operation for delay control, the pseudo differential structure regulating duty cycle reduces the jitter and also optimize the linear operating range of the voltage-controlled-delay-line, and the mixed-signal delay-locked loop embedded with dual-edge synchronization enhances the mitigation of single-event upsets. [28] The majority of techniques for mitigation of Single-Event Upsets (SEUs) on FPGAs are based on hardware spatial-redundancy. [29] Since single-event upsets (SEU) are the most important errors in microelectronic devices, in this work, the microdosimetric one-hit detector model was evaluated to determine the SEU cross-section for microelectronic devices. [30] The impact of the irradiation side on the cross sections of single-event upsets (SEUs) induced by neutrons was investigated by performing neutron irradiation measurements and simulations. [31] It may often exhibit undesired reversals of memory bits, called single-event upsets or soft errors. [32] As the technology nodes keep shrinking, single-event upsets (SEUs) may encounter more frequent multiple-bit upsets (MBUs) per particle strike. [33] Single-event upsets (SEUs) occur more frequently within large-scale deployments of SRAM-based FPGAs. [34]商用现货 (COTS) 静态随机存取存储器 (SRAM) 中的单事件翻转 (SEU) 分布通常被认为在设备中是均匀的。 [1] 这些系统容易受到可能破坏硬件配置和软件实施的单事件扰动 (SEU) 的影响。 [2] 在低能量质子（500 keV–1. [3] 在 20-nm 体平面 SRAM 中研究了负和正 μ 子诱导的单粒子翻转 (SEU)。 [4] 表征低能中子 (<10 MeV) 引起的单粒子翻转 (SEU) 和多单元翻转 (MCU) 对于验证当前地面软错误率 (SER) 标准并研究其增强情况至关重要。 [5] 这有助于增加空间应用中更高幅度的单粒子扰动 (SEU) 发生的概率。 [6] FPGA 中由辐射引起的单事件扰乱 (SEU) 的缓解通过 Xilinx 软错误缓解 (SEM) 控制器和 FPGA 固件中的三模冗余 (TMR) 方案的组合来执行。 [7] 本文研究了重离子能量和种类对最先进的 NAND 闪存中单粒子翻转 (SEU) 灵敏度的影响。 [8] 然而，基于 FPGA 的数字通道器将在空间平台上遭受单事件扰动 (SEU)。 [9] 这种滤波器的基于 SRAM 的 FPGA 实现容易受到由单事件翻转 (SEU) 引起的存储器位翻转的影响。 [10] 为此，本研究以基本数字元件，即反相器和静态随机存取存储器（SRAM）为重点，收集了单事件翻转（SEU）和单事件瞬态四个特征参数的100多组数据。 SET），这两者都是数字逻辑状态中不希望的翻转。 [11] 存储器在降低刷新率的情况下进行了测试，以暴露更多的单事件扰动，并在专门为测试设施中的此类研究开发的电路板提供的类似条件下进行测试。 [12] 然而，FPGA 已被证明容易受到辐射引起的单粒子扰动 (SEU) 的影响。 [13] 空间平台，硬件极性解码器中的存储器将遭受单事件扰乱（SEU），这可能导致故障并中断通信。 [14] 当 RS-EC 解码器在空间平台的现场可编程门阵列 (FPGA) 上实现时，它会遭受单事件扰乱 (SEU)，从而导致故障。 [15] 因此，当这些深亚微米器件用于空间环境中的存储单元时，单事件翻转（SEU），也称为软错误，对单元的可靠性构成了巨大威胁。 [16] 在高于重离子线性能量转移 (LET) 阈值的 65-nm 静态随机存取存储器 (SRAM) 中研究了离子轨迹特性对单粒子翻转 (SEU) 和多单元翻转 (MCU) 的影响。 [17] 然而，随着技术特征尺寸的不断缩小，单粒子瞬变 (SET) 和单粒子翻转 (SEU) 等单粒子效应 (SEE) 会显着导致暴露于辐射环境的数据转换器的性能下降。 [18] nan [19] nan [20] nan [21] nan [22] nan [23] nan [24] nan [25] nan [26] nan [27] nan [28] nan [29] nan [30] nan [31] nan [32] nan [33] nan [34]