Reduced Instruction(减少指令)研究综述
Reduced Instruction 减少指令 - Reduced Instruction Set Computer (RISC) is a design which presents better performances, higher speed of operation and favors the smaller and simpler set of instructions. [1] Here, low-voltage metering hardware uses Advanced Reduced Instruction Set Computing (RISC) Machines (ARM) cortex and real-time operating system. [2] This paper proposes an accelerated implementation for the DEM using Advanced of Reduced Instruction Set Computing Machine. [3] Due to high dynamic energy and long latency on write operations, Reduced Instruction Set Computing (RISC) processors cannot be employed for executing some applications as it execute more instructions at a time. [4] This paper designs and implements a dedicated microprocessor architecture based on the RISC-V (the fifth-generation Reduced Instruction Set Computing) with only 20 instructions for arbitrary-point FFT (Fast Fourier Transform) algorithm. [5] This poster presents a 32-bit Reduced Instruction Set Computer five (RISC-V) microprocessor with a COordinate Rotation DIgital Computer (CORDIC) algorithm accelerator. [6] With the utilization of strategies, for example, diminished guidance Systems on Chip (SOC, for example, to Reduced Instruction Set Computing Chips (RISC) framework, it have more space for the web of things. [7] The project uses special versions of reduced instruction set chips that are able to operate near the hot section of the engine. [8] To solve the above problem, a flexible accelerator RF-RISA, Random Forest Reduced Instruction Set Accelerator, is presented in this paper. [9] The main purpose of this paper is to design, verify and implement 16_bit RISC (Reduced Instruction Set Computer) processor that can be used for many embedded applications. [10] Enlightened by the design principle of conventional reduced instruction set computer (RISC), this article proposes a new software/hardware system for ReRAM-based NN acceleration, which achieves complex functions with sophisticated software tools while making the hardware much more compact and efficient, in order to fully utilize ReRAM potential. [11] Reduced Instruction Set Computing (RISC) processors have wide selection of applications performance on speed and better cache memory. [12] The reduced instruction set computer, or RISC, is a microprocessor that executes small and similar instructions that execute in about similar time. [13] Here we report a 32-bit Arm (a reduced instruction set computing (RISC) architecture) microprocessor developed with metal-oxide thin-film transistor technology on a flexible substrate (which we call the PlasticARM). [14] Unintended data changes can cause a serious error in reduced instruction set computer (RISC)-based small embedded systems. [15] This study used the European Health Literacy Survey Questionnaire (HLS-EU-Q16), Health Knowledge Questionnaire, Reduced Instructional Materials Motivation Survey (RIMMS), and Flow Scale as evaluation tools. [16] The instruction set has operators that most resemble a Reduced Instruction Set architecture format, and use three explicit memory operands which are sufficient for translation purposes and also simplify Symbolic Analysis. [17] Hence, this study proposes three key contributions for the challenge, namely, an algorithm framework to provide real-time epilepsy detection, a dedicated coprocessor chip implementing this framework to enable real time epilepsy detection to offload and accelerate detection algorithm, and a custom interface with the coprocessor and reduced instruction set computer-V (RISC-V) instructions to reconfigure the coprocessor and transfer data. [18]精简指令集计算机 (RISC) 是一种具有更好性能、更高运行速度并支持更小、更简单的指令集的设计。 [1] 在这里，低压计量硬件使用高级精简指令集计算 (RISC) 机器 (ARM) 皮质和实时操作系统。 [2] 本文提出了一种使用先进的精简指令集计算机器的 DEM 加速实现。 [3] 由于写操作的高动态能量和长延迟，精简指令集计算 (RISC) 处理器不能用于执行某些应用程序，因为它一次执行更多指令。 [4] 本文设计并实现了一种基于RISC-V（第五代精简指令集计算）的专用微处理器架构，其任意点FFT（快速傅里叶变换）算法只有20条指令。 [5] 此海报展示了带有坐标旋转数字计算机 (CORDIC) 算法加速器的 32 位精简指令集计算机五 (RISC-V) 微处理器。 [6] 随着策略的使用，例如减少芯片上的引导系统（SOC，例如，减少指令集计算芯片（RISC）框架），它为物联网提供了更多空间。 [7] 该项目使用能够在引擎热区附近运行的特殊版本的精简指令集芯片。 [8] 针对上述问题，本文提出了一种灵活的加速器RF-RISA，即随机森林精简指令集加速器。 [9] 本文的主要目的是设计、验证和实现可用于许多嵌入式应用的 16 位 RISC（精简指令集计算机）处理器。 [10] 本文在传统精简指令集计算机（RISC）设计原理的启发下，提出了一种新的基于 ReRAM 的神经网络加速软硬件系统，该系统通过复杂的软件工具实现复杂的功能，同时使硬件更加紧凑和高效，在为了充分利用 ReRAM 的潜力。 [11] 精简指令集计算 (RISC) 处理器在速度和更好的高速缓存内存方面具有广泛的应用性能选择。 [12] 精简指令集计算机或 RISC 是一种微处理器，它执行在大约相似的时间内执行的小而相似的指令。 [13] 在这里，我们报告了一种 32 位 Arm（一种精简指令集计算 (RISC) 架构）微处理器，该微处理器采用金属氧化物薄膜晶体管技术在柔性基板（我们称为 PlasticARM）上开发。 [14] 在基于精简指令集计算机 (RISC) 的小型嵌入式系统中，意外的数据更改可能会导致严重错误。 [15] 本研究使用欧洲健康素养调查问卷 (HLS-EU-Q16)、健康知识问卷、减少教学材料动机调查 (RIMMS) 和心流量表作为评估工具。 [16] 该指令集具有最类似于精简指令集架构格式的运算符，并使用三个显式内存操作数，这些操作数足以用于翻译目的，也简化了符号分析。 [17] 因此，本研究为该挑战提出了三个关键贡献，即提供实时癫痫检测的算法框架，实现该框架以实现实时癫痫检测以卸载和加速检测算法的专用协处理器芯片，以及与协处理器和精简指令集计算机-V (RISC-V) 指令重新配置协处理器和传输数据。 [18]
reduced instruction set
Reduced Instruction Set Computer (RISC) is a design which presents better performances, higher speed of operation and favors the smaller and simpler set of instructions. [1] Here, low-voltage metering hardware uses Advanced Reduced Instruction Set Computing (RISC) Machines (ARM) cortex and real-time operating system. [2] This paper proposes an accelerated implementation for the DEM using Advanced of Reduced Instruction Set Computing Machine. [3] Due to high dynamic energy and long latency on write operations, Reduced Instruction Set Computing (RISC) processors cannot be employed for executing some applications as it execute more instructions at a time. [4] This paper designs and implements a dedicated microprocessor architecture based on the RISC-V (the fifth-generation Reduced Instruction Set Computing) with only 20 instructions for arbitrary-point FFT (Fast Fourier Transform) algorithm. [5] This poster presents a 32-bit Reduced Instruction Set Computer five (RISC-V) microprocessor with a COordinate Rotation DIgital Computer (CORDIC) algorithm accelerator. [6] With the utilization of strategies, for example, diminished guidance Systems on Chip (SOC, for example, to Reduced Instruction Set Computing Chips (RISC) framework, it have more space for the web of things. [7] The project uses special versions of reduced instruction set chips that are able to operate near the hot section of the engine. [8] To solve the above problem, a flexible accelerator RF-RISA, Random Forest Reduced Instruction Set Accelerator, is presented in this paper. [9] The main purpose of this paper is to design, verify and implement 16_bit RISC (Reduced Instruction Set Computer) processor that can be used for many embedded applications. [10] Enlightened by the design principle of conventional reduced instruction set computer (RISC), this article proposes a new software/hardware system for ReRAM-based NN acceleration, which achieves complex functions with sophisticated software tools while making the hardware much more compact and efficient, in order to fully utilize ReRAM potential. [11] Reduced Instruction Set Computing (RISC) processors have wide selection of applications performance on speed and better cache memory. [12] The reduced instruction set computer, or RISC, is a microprocessor that executes small and similar instructions that execute in about similar time. [13] Here we report a 32-bit Arm (a reduced instruction set computing (RISC) architecture) microprocessor developed with metal-oxide thin-film transistor technology on a flexible substrate (which we call the PlasticARM). [14] Unintended data changes can cause a serious error in reduced instruction set computer (RISC)-based small embedded systems. [15] The instruction set has operators that most resemble a Reduced Instruction Set architecture format, and use three explicit memory operands which are sufficient for translation purposes and also simplify Symbolic Analysis. [16] Hence, this study proposes three key contributions for the challenge, namely, an algorithm framework to provide real-time epilepsy detection, a dedicated coprocessor chip implementing this framework to enable real time epilepsy detection to offload and accelerate detection algorithm, and a custom interface with the coprocessor and reduced instruction set computer-V (RISC-V) instructions to reconfigure the coprocessor and transfer data. [17]精简指令集计算机 (RISC) 是一种具有更好性能、更高运行速度并支持更小、更简单的指令集的设计。 [1] 在这里，低压计量硬件使用高级精简指令集计算 (RISC) 机器 (ARM) 皮质和实时操作系统。 [2] 本文提出了一种使用先进的精简指令集计算机器的 DEM 加速实现。 [3] 由于写操作的高动态能量和长延迟，精简指令集计算 (RISC) 处理器不能用于执行某些应用程序，因为它一次执行更多指令。 [4] 本文设计并实现了一种基于RISC-V（第五代精简指令集计算）的专用微处理器架构，其任意点FFT（快速傅里叶变换）算法只有20条指令。 [5] 此海报展示了带有坐标旋转数字计算机 (CORDIC) 算法加速器的 32 位精简指令集计算机五 (RISC-V) 微处理器。 [6] 随着策略的使用，例如减少芯片上的引导系统（SOC，例如，减少指令集计算芯片（RISC）框架），它为物联网提供了更多空间。 [7] 该项目使用能够在引擎热区附近运行的特殊版本的精简指令集芯片。 [8] 针对上述问题，本文提出了一种灵活的加速器RF-RISA，即随机森林精简指令集加速器。 [9] 本文的主要目的是设计、验证和实现可用于许多嵌入式应用的 16 位 RISC（精简指令集计算机）处理器。 [10] 本文在传统精简指令集计算机（RISC）设计原理的启发下，提出了一种新的基于 ReRAM 的神经网络加速软硬件系统，该系统通过复杂的软件工具实现复杂的功能，同时使硬件更加紧凑和高效，在为了充分利用 ReRAM 的潜力。 [11] 精简指令集计算 (RISC) 处理器在速度和更好的高速缓存内存方面具有广泛的应用性能选择。 [12] 精简指令集计算机或 RISC 是一种微处理器，它执行在大约相似的时间内执行的小而相似的指令。 [13] 在这里，我们报告了一种 32 位 Arm（一种精简指令集计算 (RISC) 架构）微处理器，该微处理器采用金属氧化物薄膜晶体管技术在柔性基板（我们称为 PlasticARM）上开发。 [14] 在基于精简指令集计算机 (RISC) 的小型嵌入式系统中，意外的数据更改可能会导致严重错误。 [15] 该指令集具有最类似于精简指令集架构格式的运算符，并使用三个显式内存操作数，这些操作数足以用于翻译目的，也简化了符号分析。 [16] 因此，本研究为该挑战提出了三个关键贡献，即提供实时癫痫检测的算法框架，实现该框架以实现实时癫痫检测以卸载和加速检测算法的专用协处理器芯片，以及与协处理器和精简指令集计算机-V (RISC-V) 指令重新配置协处理器和传输数据。 [17]