Plane Dislocation(平面错位)研究综述
Plane Dislocation 平面错位 - During these material defect investigations we focus on intrinsic basal-plane dislocations (BPDs), as well as on different types of stacking faults (SFs) and triangular defects. [1] To understand the effects of temperature and injection current density on expansion of Shockley stacking faults (SSFs) from basal-plane dislocations in 4H-SiC p-i-n diodes, the threshold current density for SSF expansion was investigated at eight temperatures by electroluminescence image observation. [2] The influence of basal-plane dislocation (BPD) depth on the expansion of single Shockley-type stacking faults (1SSFs) was investigated during the forward-current degradation of 4H–SiC p–i–n diodes. [3] From the present experiment, it is found that almost all basal-plane dislocations have a-type Burgers vectors, and threading dislocations have a- and (a + c)-type Burgers vectors. [4]在这些材料缺陷研究中，我们专注于本征基面位错 (BPD)，以及不同类型的堆垛层错 (SF) 和三角形缺陷。 [1] 为了了解温度和注入电流密度对 4H-SiC p-i-n 二极管中基面位错的 Shockley 堆垛层错 (SSF) 扩展的影响，通过电致发光图像观察在八个温度下研究了 SSF 扩展的阈值电流密度。 [2] 在 4H-SiC p-i-n 二极管的正向电流衰减过程中，研究了基面位错 (BPD) 深度对单个 Shockley 型堆垛层错 (1SSF) 扩展的影响。 [3] 从目前的实验中发现，几乎所有的基面位错都具有a型Burgers向量，而螺纹位错具有a型和(a + c)型Burgers向量。 [4]
Basal Plane Dislocation 基底面错位
A comparison between basal plane dislocations and threading screw dislocations in the substrate with the defects in the epitaxial layer (mainly stacking faults and carrots) was performed. [1] This implies that there are significant number of Basal Plane Dislocations (BPDs) present in these devices. [2] An etch pit sample on reproduced substrate from which epitaxial film was removed was fabricated by etching process using molten KOH+Na2O2, and some types of etch pits which might be originated from threading edge dislocations (TEDs), threading screw dislocations (TSDs) and basal plane dislocations (BPDs) in the substrate were observed. [3] Also, during the buffer layer growth a strong dependence between basal plane dislocations propagation and the growth rate has been observed. [4] 6-μm-thick N + B-doped (N: 4 × 1018 cm−3, B: 7 × 1017 cm−3) buffer layer in the PiN diode showed increased intensity of D center-related electroluminescence with increasing injected hole concentrations and prevented the formation of stacking faults from basal plane dislocations in the substrate even at the injection level of 1 × 1016 cm−3 at the interface between the drift and buffer layers. [5] As SiC power devices are being developed toward ultrahigh-voltage bipolar structures, the density of basal plane dislocations in SiC epilayers has to be minimized. [6] The electrical results presented in this work are consistent with basal plane dislocations (BPDs) that form stacking faults during forward conduction of the body-diode. [7] Photoluminescence (PL) signals from extended defects on 4H-SiC substrates were correlated to the specific etch features of Basal Plane Dislocations (BPDs), Threading Screw Dislocations (TSDs), and Threading Edge Dislocations (TED). [8] Configurations of the basal plane dislocations in 4H-SiC epitaxial layers are classified into two types, having typical combinations of ‘straight Si-core and straight C-core’ and ‘straight Si-core and curved C-core’ partial dislocations. [9] Crystal damage beneath the surface remaining after chemo-mechanical polishing (CMP) and basal plane dislocations (BPDs) of 4H-SiC epi-ready substrates have been inspected by using a mirror electron microscope inspection system non-destructively. [10] Single Shockley stacking faults (SSFs) expand from basal plane dislocations (BPDs) under forward current operation of 4H-SiC bipolar devices, giving rise to a reliability deterioration mode called “bipolar degradation”. [11] Basal plane dislocations (BPDs) in 4H silicon carbide (SiC) crystals grown using the physical vapor transport (PVT) method are diminishing the performance of SiC-based power electronic devices such as pn-junction diodes or MOSFETs. [12] Threading edge and threading screw dislocation densities increased and decreased, respectively, while basal plane dislocation densities were unaffected by the increase in growth rate. [13] The distribution of basal plane dislocations (BPDs) in physical vapor transport (PVT) grown 4H-SiC crystals has been investigated using Raman microscopy and X-ray topography. [14] A key point to achieve that is the increase of yield during epitaxial layer growth through the reduction of structural defects (such as basal plane dislocations and triangle defects), an increased thickness and doping uniformity, and a high growth rate. [15] The basal plane dislocation (BPDs) and threading screw dislocation (TSDs) cause from the seed crystal and formed at the initial stage of growth were gradually decreased in number along the length of the crystal and under certain conditions such as distorted stresses, dislocations were converted into other types of dislocations. [16] It was identified that their origins are pre-existing bar-shaped stacking faults in a SiC epi-layer, a basal plane dislocation in a SiC substrate, or a closed micropipe. [17] Basal plane dislocations are shown to increase the nonradiative recombination rate. [18] Threading edge dislocations (TEDs) and screw-type dislocations as well as {0001}-plane basal plane dislocations have been observed, and their Burgers vectors were evaluated based on the XRT contrast of these dislocations. [19] The microstructural observation confirms that the governing deformation mechanism for the carbon cathode is basal plane dislocation pile-ups and dislocation tangles at the stage of transient creep. [20] On-axis homoepitaxy of 4H-SiC has the advantage of producing epilayers that are free of basal plane dislocations. [21] Previously, the basal plane dislocation (BPD) in a SiC substrate have been reduced to suppress bipolar degradation. [22] X-ray topography revealed that there existed networks of basal plane dislocations at the growth interface, and they extended deep inside the seed crystal. [23] We studied the impact of ion implantation into the wafer substrate prior to the epitaxy process on the basal plane dislocation conversion behavior during epitaxial layer growth. [24] Direct observation of thermal gradient induced motion of basal plane dislocations by in-situ synchrotron X-ray topography imaging of PVT-grown 4H-SiC wafers subject to high temperature treatment has provided an opportunity to analyze the movement of dislocations. [25]对衬底中的基面位错和螺纹位错与外延层中的缺陷（主要是堆垛层错和胡萝卜）进行了比较。 [1] 这意味着这些设备中存在大量的基面位错 (BPD)。 [2] 使用熔融 KOH+Na2O2 蚀刻工艺在去除外延膜的复制衬底上制造蚀刻坑样品，以及可能源自螺纹刃位错 (TEDs)、螺纹螺位错 (TSDs) 和基底位错的某些类型的蚀刻坑。观察到衬底中的平面位错（BPD）。 [3] 此外，在缓冲层生长期间，已观察到基面位错传播与生长速率之间的强烈依赖性。 [4] PiN二极管中6-μm厚的N + B掺杂（N：4 × 1018 cm-3，B：7 × 1017 cm-3）缓冲层显示出随着注入空穴浓度的增加，D中心相关电致发光的强度增加，并且即使在漂移层和缓冲层之间的界面处注入水平为 1 × 1016 cm-3 的情况下，也可以防止衬底中基面位错形成堆垛层错。 [5] 随着 SiC 功率器件向超高压双极结构发展，必须尽量减小 SiC 外延层中的基面位错密度。 [6] 这项工作中呈现的电学结果与在体二极管正向传导期间形成堆垛层错的基面位错 (BPD) 一致。 [7] 来自 4H-SiC 衬底上扩展缺陷的光致发光 (PL) 信号与基底平面位错 (BPD)、螺纹位错 (TSD) 和螺纹刃位错 (TED) 的特定蚀刻特征相关。 [8] 4H-SiC外延层中的基面位错配置分为两种类型，具有“直Si核和直C核”和“直Si核和弯曲C核”部分位错的典型组合。 [9] 使用镜面电子显微镜检查系统无损检查了 4H-SiC 外延衬底的化学机械抛光 (CMP) 和基面位错 (BPD) 后残留的表面下方的晶体损伤。 [10] 单 Shockley 堆垛层错 (SSF) 在 4H-SiC 双极器件的正向电流操作下从基面位错 (BPD) 扩展，产生称为“双极退化”的可靠性劣化模式。 [11] 使用物理气相传输 (PVT) 方法生长的 4H 碳化硅 (SiC) 晶体中的基面位错 (BPD) 正在降低基于 SiC 的电力电子器件（例如 pn 结二极管或 MOSFET）的性能。 [12] 螺纹刃口和螺纹螺位错密度分别增加和减少，而基面位错密度不受生长速率增加的影响。 [13] 已经使用拉曼显微镜和 X 射线形貌研究了物理气相传输 (PVT) 生长的 4H-SiC 晶体中基面位错 (BPD) 的分布。 [14] 实现这一目标的关键是通过减少结构缺陷（例如基面位错和三角形缺陷）、增加厚度和掺杂均匀性以及高生长速率来提高外延层生长期间的产量。 [15] 由晶种引起并在生长初期形成的基面位错（BPDs）和螺纹型位错（TSDs）沿晶体长度方向逐渐减少，并且在变形应力等一定条件下，位错发生转化。成其他类型的错位。 [16] 已确定它们的起源是 SiC 外延层中预先存在的条形堆垛层错、SiC 衬底中的基面位错或闭合微管。 [17] 显示基底平面位错增加非辐射复合率。 [18] 已观察到螺纹刃型位错 (TED) 和螺旋型位错以及 {0001} 面基面位错，并根据这些位错的 XRT 对比度评估了它们的 Burgers 矢量。 [19] 微观结构观察证实，在瞬态蠕变阶段，碳阴极的主要变形机制是基面位错堆积和位错缠结。 [20] 4H-SiC 的轴上同质外延具有产生没有基面位错的外延层的优势。 [21] 以前，已经减少了 SiC 衬底中的基面位错 (BPD) 以抑制双极退化。 [22] X射线形貌显示在生长界面处存在基面位错网络，它们延伸到晶种深处。 [23] 我们研究了在外延层生长过程中，在外延工艺之前将离子注入到晶片衬底中对基面位错转换行为的影响。 [24] 通过对经高温处理的 PVT 生长的 4H-SiC 晶片进行原位同步加速器 X 射线形貌成像直接观察基面位错的热梯度引起的运动，这为分析位错的运动提供了机会。 [25]