Esd Power(防静电电源)研究综述
Esd Power 防静电电源 - Different engineered designs are proposed to mitigate turn-on vulnerability and ESD power to fail scalability, while keeping channel performance and hot carrier degradation unaffected. [1]提出了不同的工程设计来减轻开启脆弱性和 ESD 电源失效可扩展性，同时保持通道性能和热载流子退化不受影响。 [1]
Efficient Esd Power 高效的 Esd 电源
Modification of N+/P+ source segmented design of ESD nMOS shows the most efficient ESD power clamp performance in terms of It2/area and holding voltage among other design structure experiments. [1] A novel area-efficient ESD power clamp with enhanced noise immunity is proposed. [2]ESD nMOS 的 N+/P+ 源极分段设计的修改显示了在其他设计结构实验中，在 It2/面积和保持电压方面最有效的 ESD 功率钳位性能。 [1] 提出了一种具有增强抗噪能力的新型面积效率高的 ESD 电源钳位。 [2]
esd power clamp ESD 电源钳
Modification of N+/P+ source segmented design of ESD nMOS shows the most efficient ESD power clamp performance in terms of It2/area and holding voltage among other design structure experiments. [1] Fabrication-induced high-leakage issue of an overdrive ESD power clamp is presented. [2] A novel area-efficient ESD power clamp with enhanced noise immunity is proposed. [3] The paper presents the innovated methodologies by simply adding resistors and MIM capacitor to optimize ESD power clamps for high supply voltage that exceeds (generally doubles) the maximum applicable voltage for a standard CMOS process. [4] It is demonstrated that the performance of 6 $T$ SRAM and RC control ESD power clamp through the trade-off between two key design knobs of FinFET can be improved extremely with implementation of the newly proposed general compact model. [5]ESD nMOS 的 N+/P+ 源极分段设计的修改显示了在其他设计结构实验中，在 It2/面积和保持电压方面最有效的 ESD 功率钳位性能。 [1] 提出了过驱动 ESD 电源钳位的制造引起的高泄漏问题。 [2] 提出了一种具有增强抗噪能力的新型面积效率高的 ESD 电源钳位。 [3] 本文介绍了创新方法，通过简单地添加电阻器和 MIM 电容器来优化 ESD 电源钳位，以实现超过（通常是两倍）标准 CMOS 工艺的最大适用电压的高电源电压。 [4] 结果表明，通过在 FinFET 的两个关键设计旋钮之间进行权衡，6 $T$ SRAM 和 RC 控制 ESD 电源钳位的性能可以随着新提出的通用紧凑模型的实施而得到极大的改善。 [5]