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A modified pseudo 2D physically-based model for double-gate TFETs: Role of precise calculations of drain and source depletion regions


An analytical charge-based capacitance model for double-gate tunnel FETs


Design and Performance Analysis of Advanced MOSFET Structures



Investigation of Variability in Device Design on Saturation Characteristics of Nanowire Tunnel FETs



Triple Metal Surrounding Gate Junctionless Tunnel FET based 6T SRAM Design For Low Leakage Memory System



Re-Assessment of Steep-Slope Device Design From a Circuit-Level Perspective Using Novel Evaluation Criteria and Model-Less Method



Triple Metal Surrounding Gate Junctionless Tunnel FET Based 6T SRAM Design for Low Leakage Memory System


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10.1109/SNW51795.2021.00043

High-temperature operation of silicon spin qubits up to 10 K with employing isoelectronic-trap-assisted tunnel FETs



Investigation of Variation in Device Design Parameters on the Saturation Voltages of Hetero-junction Nanowire Tunnel FETs



Using Anisotropic Insulators to Engineer the Electrostatics of Conventional and Tunnel Field-Effect Transistors


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10.1007/978-3-319-90385-9_6

Emerging Steep-Slope Devices and Circuits: Opportunities and Challenges



Large Variation in Temperature Dependence of Band-to-Band Tunneling Current in Tunnel Devices



An Accurate Analytical Model for Tunnel FET Output Characteristics


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10.1109/PIERS-Spring46901.2019.9017652

Study of Piezoelectric-mechanical Properties of III-V Nitride Based Tunnel FET


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10.1109/ICIPRM.2019.8819239

All solid-state 2D tunnel FET



Effects of asymmetric underlap spacers on nanoscale junctionless transistors and design of optimised CMOS amplifiers


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10.1109/DRC46940.2019.9046468

InP MOSFETs Exhibiting Record 70 mV/dec Subthreshold Swing


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10.1109/DRC46940.2019.9046420

Tunnel FETs using Phosphorene/ReS2 heterostructures


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10.1109/SISPAD.2019.8870406

Full band quantum transport modelling with EP and NEGF methods; application to nanowire transistors


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