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A Digitally-Calibrated 70.98dB-SNDR 625kHz-Bandwidth Temperature-Tolerant 2nd-order Noise-Shaping SAR ADC in 65nm CMOS


3.5 A 0.6V 13b 20MS/s Two-Step TDC-Assisted SAR ADC with PVT Tracking and Speed-Enhanced Techniques

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10.1109/CICC51472.2021.9431415

A 94.1 dB DR 4.1 nW/Hz Bandwidth/Power Scalable DTDSM for IoT Sensing Applications Based on Swing-Enhanced Floating Inverter Amplifiers


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10.1109/lssc.2021.3119641

A 0.6-V 86.5-dB DR 40-kHz BW Inverter-Based Continuous-Time Delta–Sigma Modulator With PVT-Robust Body-Biasing


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10.1109/JSSC.2021.3053893

A 4-GS/s 10-ENOB 75-mW Ringamp ADC in 16-nm CMOS With Background Monitoring of Distortion


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10.1109/JSSC.2020.3044896

A 440-μW, 109.8-dB DR, 106.5-dB SNDR Discrete-Time Zoom ADC With a 20-kHz BW


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10.1109/JSSC.2020.3044831

A 1-MS/s to 1-GS/s Ringamp-Based Pipelined ADC With Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16 nm


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10.1109/ISCAS51556.2021.9401569

A Zero-Crossing-Based Integrator with Bidirectional Two-Phase Charging and Selective-Reset Operations for ΔΣ ADCs


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10.1016/J.MEJO.2021.105120

A 1 GS/s 10bit SAR ADC with background calibration in 28 nm CMOS


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10.1109/LSSC.2021.3092020

A 94.2-dB SNDR 142.6-μW VCO-Based Audio ADC With a Split-ADC Differential Pulse Code Modulation Architecture


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10.1109/LSSC.2021.3071965

A 65-nm CMOS Continuous-Time Pipeline ADC Achieving 70-dB SNDR in 100-MHz Bandwidth


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10.1109/ISSCC42613.2021.9365985

28.4 A 400mVpp 92.3 dB-SNDR 1kHz-BW 2nd-Order VCO-Based ExG-to-Digital Front-End Using a Multiphase Gated-Inverted Ring-Oscillator Quantizer


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10.23919/VLSICircuits52068.2021.9492383

A 300MHz-BW 38mW 37dB/40dB SNDR/DR Frequency-Interleaving Continuous-Time Bandpass Delta-Sigma ADC in 28nm CMOS


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10.1109/ISSCC42613.2021.9366006

10.3 A 100MHz-BW 68dB-SNDR Tuning-Free Hybrid-Loop DSM with an Interleaved Bandpass Noise-Shaping SAR Quantizer


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10.1109/jssc.2021.3112635

A 178.9-dB FoM 128-dB SFDR VCO-Based AFE for ExG Readouts With a Calibration-Free Differential Pulse Code Modulation Technique


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10.1109/JSSC.2020.3032152

A 134-μW 99.4-dB SNDR Audio Continuous-Time Delta-Sigma Modulator With Chopped Negative-R and Tri-Level FIR-DAC


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10.1109/ISCAS51556.2021.9401115

A 1st-Order Passive Noise-Shaping SAR ADC with Improved NTF Assisted by Comparator Gain Calibration


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10.1109/ISSCC42613.2021.9365833

27.6 A 25MHz-BW 75dB-SNDR Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC with Background Offset Calibration


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10.1108/cw-12-2020-0356

A 10-bit 200 MS/s pipelined ADC with parallel sampling and switched op-amp sharing technique


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10.1109/JSSC.2020.3025605

A 4-GS/s 11.3-mW 7-bit Time-Based ADC With Folding Voltage-to-Time Converter and Pipelined TDC in 65-nm CMOS


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10.1109/JSSC.2020.3017229

A 15.1-mW 6-GS/s 6-bit Single-Channel Flash ADC With Selectively Activated 8× Time-Domain Latch Interpolation


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10.1109/ISSCC42613.2021.9365807

10.1 A 116μ W 104.4dB-DR 100.6dB-SNDR CT Δ∑ Audio ADC Using Tri-Level Current-Steering DAC with Gate-Leakage Compensated Off-Transistor-Based Bias Noise Filter


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10.1109/TVLSI.2021.3078689

A 13-bit 312.5-MS/s Pipelined SAR ADC With Open-Loop Integrator-Based Residue Amplifier and Gain-Stabilized Integration Time Generation


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10.1109/A-SSCC47793.2019.9056891

A High DR High-Input-Impedance Programmable-Gain ECG Acquisition Interface with Non-inverting Continuous Time Sigma-Delta Modulator


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10.1109/cicc.2018.8357056

A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers


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10.1109/MWSCAS.2019.8885366

A Highly Digital CCO-Based Asynchronous Analog-to-Time Converter


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10.1109/ISCAS.2019.8702299

An 8-bit 80-MS/s Fully Self-Timed SAR ADC with 3/2 Interleaved Comparators and High-Order PVT Stabilized HBT Bandgap Reference


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10.1109/TNSRE.2019.2929081

Compact and Low-Power Neural Spike Compression Using Undercomplete Autoencoders


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10.1109/ISSCC.2019.8662524

3.2 A 7.6mW 1GS/s 60dB SNDR Single-Channel SAR-Assisted Pipelined ADC with Temperature-Compensated Dynamic Gm-R-Based Amplifier


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10.1109/TCSI.2019.2898415

Highly Digital Second-Order $\Delta\Sigma$ VCO ADC


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10.1109/ISSCC.2019.8662317

20.7 A 72.6dB-SNDR 100MHz-BW 16.36mW CTDSM with Preliminary Sampling and Quantization Scheme in Backend Subranging QTZ


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10.1109/JSSC.2018.2889680

A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers


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10.23919/VLSIC.2019.8778032

A 75.8dB-SNDR Pipeline SAR ADC with 2nd-order Interstage Gain Error Shaping


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10.1007/S10470-019-01406-0

2+2 MASH incremental ADC


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10.1109/EDSSC.2019.8753967

A high speed fully self-timed SAR ADC with an on-chip adaptative reference buffer


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10.1109/ICCT46805.2019.8946997

A 78.20dB SNDR CT Sigma-Delta Modulator Achieving 40.6fJ/conv


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10.1109/ISCAS.2019.8702573

Double-Comparison Settling Error Correction Scheme for Binary Scaled SAR ADCs


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10.1109/JSSC.2018.2879923

A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS


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10.1109/TCSII.2018.2855962

A 21-GS/s Single-Bit Second-Order Delta–Sigma Modulator for FPGAs


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10.1109/CICC.2019.8780368

A 40/30 MS/s Dual-Mode Pipelined ADC with Error Averaging Techniques in 90nm CMOS Achieving 71.2/74.5 dB SNDR over the Entire Nyquist Bandwidth


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10.1109/LSSC.2019.2927834

A 4-GS/s 39.9-dB SNDR 11.7-mW Hybrid Voltage–Time Two-Step ADC With Feed-Forward Ring Oscillator-Based TDCs


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10.1109/JSSC.2019.2930903

A High DR, DC-Coupled, Time-Based Neural-Recording IC With Degeneration R-DAC for Bidirectional Neural Interface


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10.1109/TCSII.2018.2828649

A 10-Bit 600-MS/s Time-Interleaved SAR ADC With Interpolation-Based Timing Skew Calibration


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10.1109/CICC.2019.8780169

A Generated 7GS/s 8b Time-Interleaved SAR ADC with 38.2dB SNDR at Nyquist in 16nm CMOS FinFET


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10.1109/TCSII.2018.2847402

A Highly Digital ADC With Enhanced Accuracy Using a Simple Ripple-Transferring Replica Pseudo PLL Technique


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10.1109/CICC.2019.8780191

A 7b 2.6mW 900MS/s Nonbinary 2-then-3b/cycle SAR ADC with Background Offset Calibration


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10.1109/MWSCAS.2019.8884940

A Single Channel Bandpass SAR ADC with Digitally Assisted NTF Re-configuration


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10.1109/CICC.2019.8780180

A 2-way 7.3-bit 10 GS/s Time-based Folding ADC with Passive Pulse-Shrinking Cells


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10.1109/CICC.2019.8780175

A 0.025-mm2 0.8-V 78.5dB-SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣM Structure


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10.1109/ESSCIRC.2019.8902671

A 4-GS/s 39.9-dB SNDR 11.7-mW Hybrid Voltage–Time Two-Step ADC With Feed-Forward Ring Oscillator-Based TDCs


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10.1109/CICC.2019.8780222

A 10b 1.6GS/s 12.2mW 7/8-way Split Time-interleaved SAR ADC with Digital Background Mismatch Calibration


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10.1016/J.AEUE.2018.12.005

A CT ΔΣ modulator using 4-bit asynchronous SAR quantizer and MPDWA DEM


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10.1109/TCSI.2019.2894034

An 85-MHz-BW ASAR-Assisted CT 4-0 MASH $\Delta\Sigma$ Modulator With Background Half-Range Dithering-Based DAC Calibration in 28-nm CMOS


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10.1109/JSSC.2018.2889847

Inverter-Based Subthreshold Amplifier Techniques and Their Application in 0.3-V $\Delta\Sigma$ -Modulators


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