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A 0.6 V, 2nd order low-pass Gm-C filter using CMOS inverter-based tunable OTA with 1.114 GHz cut-off frequency in 90nm CMOS technology

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Design of Low Power CMOS Based Schmitt Trigger in 180nm Technology

Design of CMOS Based D Flip-Flop with Different Low Power Techniques

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Back-End-of-Line Compatible Fully Depleted CMOS Inverters Employing Ge p-FETs and α-InGaZnO n-FETs

Improved digital performance of hybrid CMOS inverter with Si p-MOSFET and InGaAs n-MOSFET in the nanometer regime

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Proceedings of International Conference on Communication, Circuits, and Systems: IC3S 2020

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Novel Memristor-based Nonvolatile D Latch and Flip-flop Designs

Performance Projection of 2-D Material-Based CMOS Inverters for Sub-10-nm Channel Length

Design and Performance Analysis of 4-bit Nano-processor Design for Low Area, Low Power and Minimum Delay Using 32nm FinFET Technology

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High Voltage Gain 4H-SIC CMOS Technology Featuring LOCal Oxidation of SiC (LOCOSiC) Isolation and Balanced Gate Dielectric

Printed solid state electrolyte carbon nanotube thin film transistors for sub-1 V fully printed flexible CMOS inverters

Sizing techniques for delay optimisation of 4-bit dynamic CMOS Manchester carry chain

NBTI stress delay sensitivity analysis of reliability enhanced Schmitt trigger based circuits

Design and simulation of tunable low-pass Gm-C filter with 1 GHz cutoff frequency based on CMOS inventers for high speed telecommunication applications

Performance of Ge p-channel junctionless FinFETs for logic applications

Research on Relationship Between Transistor Size and DC Noise Margin of CMOS Inverter

A 200-pA Under-Voltage Lockout Circuit for Ultra-Low Power Applications

Digital RF Transmitter With Single-Bit $\Delta\Sigma$ M-Driven Switched-Capacitor RF DAC and Embedded Band Filter in 28-nm FD-SOI

Design and analysis of low power high-speed 1-bit full adder cells for VLSI applications

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Improving 5V Digital 4H-SiC CMOS ICs for Operating at 400°C Using PMOS Channel Implantation

Impacts of atomistic surface roughness on electronic transport in n-type and p-type MoS2 field-effect transistors

Reconfigurable arithmetic logic unit designed with threshold logic gates

Fabrication of $\Omega$ -gated Negative Capacitance FinFETs and SRAM

Chemically Tuned p- and n-Type WSe2 Monolayers with High Carrier Mobility for Advanced Electronics.

A Thomas Algorithm-Based Generic Approach for Modeling of Power Supply Induced Jitter in CMOS Buffers

First Demonstration of CMOS Inverter and 6T-SRAM Based on GAA CFETs Structure for 3D-IC Applications

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Cmos Inverters CMOS 인버터

Cmos Inverters CMOS 인버터
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