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Performance Comparison of Radix-2 FFT Butterfly Unit with Baugh Wooley and Modified Baugh Wooley


Hardware Implementation of FFT/IFFT Algorithms Incorporating Efficient Computational Elements


ASIC Design of Butterfly Unit Based on Non-Redundant and Redundant Algorithm



Linear and quadratic time frequency transforms on FPGA using folding technique



Designing of Radix-2 Butterfly for Digital Signal Processor for FFT Computation



Towards Collaborative Intelligence Friendly Architectures for Deep Learning


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10.1109/ASICON47005.2019.8983511

The Design and Implementation of High Speed Hybrid Radices Reconfigurable FFT Processor


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