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10.1109/TCSI.2020.3046524

LAYout with Gridded Objects (LAYGO), a Python-based layout-generation engine for enhancing the design productivity of custom circuit layouts in advanced CMOS processes, is presented and verified by implementing a time-interleaved SAR (TI-SAR) ADC instance in a 16 nm CMOS FinFET technology.

LAYGO: A Template-and-Grid-Based Layout Generation Engine for Advanced CMOS Technologies

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10.1109/MWSCAS.2019.8885387

A new amplifying strategy for driving time-interleaved SAR ADC (TI-SAR) is also proposed to address the stability problem of a ring amplifier.

A Ring Amplifier Based Current Feedback Continuous Time PGA for High Frequency Ultrasound Applications

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10.1109/LSSC.2019.2953840

Receiver analog signal conditioning is limited to 8-dB of peaking provided by a low-distortion analog frontend that feeds a 28-GS/s 8-bit ADC implemented as an 8-way time-interleaved SAR-ADC array.

A 56-Gb/s Long-Reach Fully Adaptive Wireline PAM-4 Transceiver in 7-nm FinFET

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10.1109/LSSC.2019.2931440

An 8-bit 10-GHz <inline-formula> <tex-math notation="LaTeX">$8\times $ </tex-math></inline-formula> time-interleaved SAR ADC in 28-nm CMOS incorporates an aggressively scaled DAC with grouped capacitors in a symmetrical comb structure to afford a threefold reduction in the bottom-plate parasitic capacitance.

An 8-bit 10-GHz 21-mW Time-Interleaved SAR ADC With Grouped DAC Capacitors and Dual-Path Bootstrapped Switch

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10.1109/CICC.2019.8780349

We have developed various complex circuit generators as driving examples, including a time-interleaved SAR ADC and a SerDes transceiver frontend.

BAG: A Process-Portable Framework for Generator-based AMS Circuit Design

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10.1109/CICC.2019.8780169

This paper presents a 7GS/s 8-bit time-interleaved SAR ADC instance produced from a generator-based design flow in a 16nm CMOS FinFET technology.

A Generated 7GS/s 8b Time-Interleaved SAR ADC with 38.2dB SNDR at Nyquist in 16nm CMOS FinFET

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10.1109/ESSCIRC.2019.8902620

4 GS/s 10-bit time-interleaved SAR ADC is presented.

A 2.4 GS/s 10-Bit Time-Interleaved SAR ADC with a Bypass Window and Opportunistic Offset Calibration

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10.1109/ESSCIRC.2019.8902621

An 8-bit 10-GHz 8× time-interleaved SAR ADC in 28-nm CMOS incorporates an aggressively scaled DAC with grouped capacitors in a symmetrical comb structure to afford a threefold reduction in the bottom-plate parasitic capacitance.

An 8-bit 10-GHz 21-mW Time-Interleaved SAR ADC With Grouped DAC Capacitors and Dual-Path Bootstrapped Switch

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10.23919/VLSIC.2019.8778077

This paper presents a 5GS/s 16-way Time-Interleaved SAR ADC in 28nm CMOS, proposing a fully-digital background timing-skew calibration based on digital mixing, without adding any extra analog circuits.

A 29mW 5GS/s Time-interleaved SAR ADC achieving 48.5dB SNDR With Fully-Digital Timing-Skew Calibration Based on Digital-Mixing

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Time Interleaved Sar - LAYout with Gridded Objects (LAYGO), a Python-based layout-generation engine for enhancing the design productivity of custom circuit layouts in advanced CMOS processes, is presented and verified by implementing a time-interleaved SAR (TI-SAR) ADC instance in a 16 nm CMOS FinFET technology. [1] A new amplifying strategy for driving time-interleaved SAR ADC (TI-SAR) is also proposed to address the stability problem of a ring amplifier. [2] Receiver analog signal conditioning is limited to 8-dB of peaking provided by a low-distortion analog frontend that feeds a 28-GS/s 8-bit ADC implemented as an 8-way time-interleaved SAR-ADC array. [3] An 8-bit 10-GHz $8\times $ time-interleaved SAR ADC in 28-nm CMOS incorporates an aggressively scaled DAC with grouped capacitors in a symmetrical comb structure to afford a threefold reduction in the bottom-plate parasitic capacitance. [4] We have developed various complex circuit generators as driving examples, including a time-interleaved SAR ADC and a SerDes transceiver frontend. [5] This paper presents a 7GS/s 8-bit time-interleaved SAR ADC instance produced from a generator-based design flow in a 16nm CMOS FinFET technology. [6] 4 GS/s 10-bit time-interleaved SAR ADC is presented. [7] An 8-bit 10-GHz 8× time-interleaved SAR ADC in 28-nm CMOS incorporates an aggressively scaled DAC with grouped capacitors in a symmetrical comb structure to afford a threefold reduction in the bottom-plate parasitic capacitance. [8] This paper presents a 5GS/s 16-way Time-Interleaved SAR ADC in 28nm CMOS, proposing a fully-digital background timing-skew calibration based on digital mixing, without adding any extra analog circuits. [9]
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