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10.1109/TVLSI.2019.2909671

A case study of an 11-bit 100-MS/s SAR ADC in 65-nm CMOS is presented.

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10.1109/CICC.2019.8780273

This paper presents a 10-bit 120MS/s SAR ADC.

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10.1109/ISSCC.2019.8662416

11ax RX analog baseband realized by a single filtering $\Delta \Sigma $ ADC [3] that uses a 6b 960MS/s SAR-quantizer combined with both low-latency DAC-segmentation (LLDS) functionality and excess-loop delay compensation (ELDC) [4].

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10.1109/ISCAS.2019.8702557

To validate these concepts, a 10-bit 2 MS/s SAR ADC is designed using 130nm CMOS process with 0.

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10.1109/CICC.2019.8780319

This work presents a small-size 10b 10MS/s SAR ADC with an integrated passive anti-aliasing filter, consuming 39.

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10.1109/NORCHIP.2019.8906906

The post-layout simulations show that the proposed design increases the signal-to-noise-and-distortion ratio of the presented 9-bit 200 MS/s SAR ADC in 65 nm CMOS by 3.

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Ms S Sar

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Apr 02, 2023

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Ms S Sar - A case study of an 11-bit 100-MS/s SAR ADC in 65-nm CMOS is presented. ^[1] This paper presents a 10-bit 120MS/s SAR ADC. ^[2] 11ax RX analog baseband realized by a single filtering $\Delta \Sigma $ ADC [3] that uses a 6b 960MS/s SAR-quantizer combined with both low-latency DAC-segmentation (LLDS) functionality and excess-loop delay compensation (ELDC) [4]. ^[3] To validate these concepts, a 10-bit 2 MS/s SAR ADC is designed using 130nm CMOS process with 0. ^[4] This work presents a small-size 10b 10MS/s SAR ADC with an integrated passive anti-aliasing filter, consuming 39. ^[5] The post-layout simulations show that the proposed design increases the signal-to-noise-and-distortion ratio of the presented 9-bit 200 MS/s SAR ADC in 65 nm CMOS by 3. ^[6]