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An Efficient and High-Speed Overlap-Free Karatsuba-Based Finite-Field Multiplier for FGPA Implementation



Physical implementation of asynchronous cellular automata networks: mathematical models and preliminary experimental results


Fpga Devices sentence examples within Modern Fpga Devices



Utilizing and Extending Trusted Execution Environment in Heterogeneous SoCs for a Pay-Per-Device IP Licensing Scheme



Improving HW/SW Adaptability for Accelerating CNNs on FPGAs Through A Dynamic/Static Co-Reconfiguration Approach


Fpga Devices sentence examples within Xilinx Fpga Devices



Modular transformation of embedded systems from firm-cores to soft-cores



Low latency Montgomery multiplier for cryptographic applications




Fpga Devices sentence examples within End Fpga Devices



A novel hardware-oriented ultra-high-speed object detection algorithm based on convolutional neural network



FPGA-based Acceleration of FT Convolution for Pulsar Search Using OpenCL


Fpga Devices sentence examples within Soc Fpga Devices



Artificial Intelligence in Electric Machine Drives: Advances and Trends



The Security of ARM TrustZone in a FPGA-Based SoC


Fpga Devices sentence examples within Variou Fpga Devices



On-The-Fly Key Generation Based VLSI Implementation of Advanced Encryption Standard



SPAGHETTI: Streaming Accelerators for Highly Sparse GEMM on FPGAs


Fpga Devices sentence examples within Intel Fpga Devices



A Cross-Platform OpenVX Library for FPGA Accelerators



Towards Prototyping and Acceleration of Java Programs onto Intel FPGAs


Fpga Devices sentence examples within Artix Fpga Devices



High-performance Pipelined FPGA Implementation of the Elliptic Curve Cryptography over GF (2n)



A Reconfigurable Implementation of Elliptic Curve Cryptography over GF (2n)


Fpga Devices sentence examples within Cost Fpga Devices



An FPGA-Based On-Device Reinforcement Learning Approach using Online Sequential Learning



ZyNet: Automating Deep Neural Network Implementation on Low-Cost Reconfigurable Edge Computing Platforms


Fpga Devices sentence examples within Acros Fpga Devices



The TaPaSCo Open-Source Toolflow



The TaPaSCo Open-Source Toolflow for the Automated Composition of Task-Based Parallel Reconfigurable Computing Systems


Fpga Devices sentence examples within Two Fpga Devices



Mix and Match: A Novel FPGA-Centric Deep Neural Network Quantization Framework



SkyCastle: A Resource-Aware Multi-Loop Scheduler for High-Level Synthesis


Fpga Devices sentence examples within Power Fpga Devices



Exploration of Hardware Acceleration Methods for an XNOR Traffic Signs Classifier



Software-Defined FPGA Accelerator Design for Mobile Deep Learning Applications


Fpga Devices sentence examples within Art Fpga Devices



Novel Reconfigurable Hardware Systems for Tumor Growth Prediction



Performance of a high-throughput tracking processor implemented on Stratix-V FPGA


Fpga Devices sentence examples within fpga devices provide



FPGA Implementation of PIR based security alert system using BASYS 3 kit



Analysis and Optimization of I/O Cache Coherency Strategies for SoC-FPGA Device


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10.1109/TVLSI.2021.3058509

An Efficient and High-Speed Overlap-Free Karatsuba-Based Finite-Field Multiplier for FGPA Implementation


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10.1109/ASAP52443.2021.00020

An Efficient Real-Time Object Detection Framework on Resource-Constricted Hardware Devices via Software and Hardware Co-design


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10.1109/ICCES51350.2021.9489090

On-The-Fly Key Generation Based VLSI Implementation of Advanced Encryption Standard


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10.1007/s11265-021-01640-8

The TaPaSCo Open-Source Toolflow


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10.1109/ICCES51350.2021.9489097

A Compact & Low Power Architecture of XXTEA192 Lightweight block cipher



Novel Reconfigurable Hardware Systems for Tumor Growth Prediction


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10.1109/HPCA51647.2021.00027

Mix and Match: A Novel FPGA-Centric Deep Neural Network Quantization Framework


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10.22055/JAREE.2021.36116.1015

A Novel 2-D BWA-MEM FPGA Accelerator for Short-Read Mapping of the Whole Human Genome


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10.1109/TC.2020.3001170

High-Performance Constant-Time Discrete Gaussian Sampling


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10.1145/3479876.3481593

Worst-case latency analysis for the versal NoC network packet switch


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10.1109/ISVLSI51109.2021.00058

New Security Threats on FPGAs: From FPGA Design Tools Perspective


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10.1145/3432261.3432266

Performance Evaluation of OpenCL-Enabled Inter-FPGA Optical Link Communication Framework CIRCUS and SMI


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10.1007/978-3-030-70665-4_60

An FPGA Implementation of Rapid Switch Module for EtherCAT Slave Controller


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10.1109/TIFS.2021.3058777

Utilizing and Extending Trusted Execution Environment in Heterogeneous SoCs for a Pay-Per-Device IP Licensing Scheme


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10.1109/PEMC48073.2021.9432622

Power Converter Half-bridge Models in the Light of Real-time FPGA Implementation


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10.1088/1748-0221/16/06/P06041

Accessing register spaces in FPGAs within the ATLAS DAQ scheme via the SCA eXtension


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10.1016/J.VLSI.2021.06.001

FPGA-based Physical Unclonable Functions: A comprehensive overview of theory and architectures


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10.1109/SSD52085.2021.9429338

An approach for an efficient sharing of IP as a Service in cloud FPGA


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10.1007/s11071-021-06754-z

Physical implementation of asynchronous cellular automata networks: mathematical models and preliminary experimental results


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10.1109/ISCA52012.2021.00044

Hetero-ViTAL: A Virtualization Stack for Heterogeneous FPGA Clusters


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10.1109/PDP52278.2021.00020

A Cross-Platform OpenVX Library for FPGA Accelerators


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10.1109/DFT52944.2021.9568280

Analyzing the Single Event Upset Vulnerability of Binarized Neural Networks on SRAM FPGAs


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10.1109/IPDPSW52791.2021.00022

An FPGA-Based On-Device Reinforcement Learning Approach using Online Sequential Learning


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10.1504/ijes.2021.10039156

Modular transformation of embedded systems from firm-cores to soft-cores


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10.1109/TNS.2021.3086408

A Comprehensive Comparison Between Design for Testability Techniques for Total Dose Testing of Flash-Based FPGAs


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10.1109/TPDS.2020.3047966

Accelerating End-to-End Deep Learning Workflow With Codesign of Data Preprocessing and Scheduling


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10.3390/electronics10202546

Hardware Implementation Study of Particle Tracking Algorithm on FPGAs


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10.36227/TECHRXIV.14445420.V1

Fixed Point Processing of the SAR Back Projection Algorithm on FPGA


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10.1145/3431920.3439459

LEAP: A Deep Learning based Aging-Aware Architecture Exploration Framework for FPGAs


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10.36227/techrxiv.16782748

Artificial Intelligence in Electric Machine Drives: Advances and Trends


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10.1109/FPL53798.2021.00053

Optimizing Deep Learning Decoders for FPGA Implementation


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10.11591/IJAI.V10.I1.PP131-138

Implementation of decision tree algorithm on FPGA devices


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10.1109/AEMCSE51986.2021.00259

Reliability improvement scheme of DDR controller based on FPGA


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10.1109/DTIS53253.2021.9505064

Memory Encryption Support for an FPGA-based RISC-V Implementation


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10.1109/TPDS.2020.3046762

Improving HW/SW Adaptability for Accelerating CNNs on FPGAs Through A Dynamic/Static Co-Reconfiguration Approach


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10.36227/TECHRXIV.14330045.V1

Exploration of Hardware Acceleration Methods for an XNOR Traffic Signs Classifier


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10.32620/REKS.2021.1.11

Hyper redundancy for super reliable FPGAs


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10.1109/TVLSI.2021.3064639

Real-Time SSDLite Object Detection on FPGA



The semantics of shared memory in Intel CPU/FPGA systems



Low latency Montgomery multiplier for cryptographic applications


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10.1186/s42400-021-00082-w

A secure and highly efficient first-order masking scheme for AES linear operations


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10.1051/epjconf/202125104016

A real-time FPGA-based cluster finding algorithm for LHCb silicon pixel detector


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10.1109/HPCA51647.2021.00017

SPAGHETTI: Streaming Accelerators for Highly Sparse GEMM on FPGAs


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10.1109/CSNT51715.2021.9509637

Design of Thermal-Aware and Power-Efficient LFSR on Different Nanometer Technology FPGA for Green Communication


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10.1109/TCAD.2020.3011650

Cheetah: An Accurate Assessment Mechanism and a High-Throughput Acceleration Architecture Oriented Toward Resource Efficiency


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10.1109/TNS.2019.2915207

Ultrahigh Energy Heavy Ion Test Beam on Xilinx Kintex-7 SRAM-Based FPGA



A PCA and Mahalanobis distance‐based detection method for logical hardware Trojan


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10.1109/VTS.2019.8758645

ZeroScreen: A Novel Structure for IC Reliability Screening at Time-Zero


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10.1145/3316781.3317829

FPGA/DNN Co-Design: An Efficient Design Methodology for 1oT Intelligence on the Edge


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10.1016/J.NIMA.2018.10.173

The algorithm of the CMS Level-1 Overlap Muon Track Finder trigger


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10.1109/FPL.2019.00067

Preallocating Resources for Distributed Memory Based FPGA Debug


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10.1109/ISSPIT47144.2019.9001747

Role of FPGA in Internet of Things Applications



Charge-Line Dual-FET High-Repetition-Rate Pulsed Laser Driver



The contribution of research platforms to the pathway from off-line to real-time high-frame-rate imaging


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10.1109/CADSM.2019.8779336

ARUZ - Analyzer of Real Complex Systems


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10.1109/FCCM.2019.00051

Towards Prototyping and Acceleration of Java Programs onto Intel FPGAs


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10.1007/s11554-019-00931-5

A novel hardware-oriented ultra-high-speed object detection algorithm based on convolutional neural network


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10.1007/s11227-019-02768-y

Cooperative CPU, GPU, and FPGA heterogeneous execution with EngineCL


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10.1016/j.ifacol.2019.12.559

Use embedded DSP blocks to implement a PID regulator


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High-performance Pipelined FPGA Implementation of the Elliptic Curve Cryptography over GF (2n)


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10.1016/j.micpro.2018.11.001

Radix-10 decimal logarithm by direct selection for 6-input LUTs programmable devices


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10.1109/TNS.2019.2920449

Worst Case Test Vectors for Sequential Circuits in Flash-Based FPGAs Exposed to Total Dose


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10.1109/ICFPT47387.2019.00058

ZyNet: Automating Deep Neural Network Implementation on Low-Cost Reconfigurable Edge Computing Platforms


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10.23919/MIPRO.2019.8756787

A New Low-Complexity Cipher Class for Clone-Resistant Identities


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10.1145/3289602.3293908

Network-on-Chip Programmable Platform in VersalTM ACAP Architecture


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10.15406/ijbsbe.2019.05.00147

A pulse sensor interface design for FPGA based multisensor health monitoring platform


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10.1109/MIEL.2019.8889599

On the Ballistic Transport in Si Nano-Devices


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10.1016/j.micpro.2019.102881

An efficient non-separable architecture for Haar wavelet transform with lifting structure


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10.1007/978-3-030-17227-5_16

The TaPaSCo Open-Source Toolflow for the Automated Composition of Task-Based Parallel Reconfigurable Computing Systems


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10.1145/3289602.3293981

PVT-Aware Sensing and Voltage Scaling for Energy Efficient FPGAs


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10.1051/ITMCONF/20192801014

Implementation of a rotor position determination system for a switched reluctance motor in FPGA devices


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10.1007/978-3-030-52686-3_4

A Reconfigurable Implementation of Elliptic Curve Cryptography over GF (2n)


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