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FPGA/DNN Co-Design: An Efficient Design Methodology for 1oT Intelligence on the Edge



Dr. BFS: Data Centric Breadth-First Search on FPGAs


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Exact and Heuristic Allocation of MuIti-kernel Applications to Multi-FPGA Platforms



Improved Techniques for Sensing Intra-Device Side Channel Leakage


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Leakier Wires



A New Pay-Per-Use Scheme for the Protection of FPGA IP



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IP Cores for Graph Kernels on FPGAs



In-memory database acceleration on FPGAs: a survey


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10.1145/3316781.3317821

Exact and Heuristic Allocation of MuIti-kernel Applications to Multi-FPGA Platforms


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10.1109/ASAP.2019.00-42

Efficient Weight Reuse for Large LSTMs


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10.1145/3316781.3317829

FPGA/DNN Co-Design: An Efficient Design Methodology for 1oT Intelligence on the Edge


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10.35940/ijitee.a9110.119119

Implementation of Area optimized Low power Multiplication and Accumulation


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10.1109/SpaceComp.2019.00008

Neutron Radiation Testing of Fault Tolerant RISC-V Soft Processor on Xilinx SRAM-based FPGAs


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10.1109/WD.2019.8734199

An FPGA Design Technique to Receive Multiple Wireless Protocols with the Same RF Front End


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10.1109/DSD.2019.00101

High-Throughput BitPacking Compression


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10.1145/3297858.3304028

Packing Sparse Convolutional Neural Networks for Efficient Systolic Array Implementations: Column Combining Under Joint Optimization


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10.1109/ITC44170.2019.9000145

FPGA Bitstream Security: A Day in the Life


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10.1145/3289602.3293948

A Pixel-Parallel Virtual-Image Architecture for High Performance and Power Efficient Graph Cuts Inference


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10.1109/DSD.2019.00103

Fault Tolerant FPGAs: Where to Spend the Effort?


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10.1007/978-3-030-17227-5_16

The TaPaSCo Open-Source Toolflow for the Automated Composition of Task-Based Parallel Reconfigurable Computing Systems


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10.1007/978-981-10-8776-9_15

SOC Prototyping and Debug Techniques



Leakier Wires


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10.1007/978-3-030-17227-5_9

(ReCo)Fuse Your PRC or Lose Security: Finally Reliable Reconfiguration-Based Countermeasures on FPGAs


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10.14569/ijacsa.2019.0100407

Fault Injection and Test Approach for Behavioural Verilog Designs using the Proposed RASP-FIT Tool


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10.1145/3299874.3318030

Thermal Fingerprinting of FPGA Designs through High-Level Synthesis


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10.1109/DFT.2019.8875431

Scatter Scrubbing: A Method to Reduce SEU Repair Time in FPGA Configuration Memory


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10.1016/J.JPDC.2019.04.002

Secure hardware-entangled field programmable gate arrays


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10.1145/3316781.3317802

Dr. BFS: Data Centric Breadth-First Search on FPGAs


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10.1109/ASAP.2019.00-25

FPGA Architectures for Real-time Dense SLAM


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10.1109/HPEC.2019.8916363

IP Cores for Graph Kernels on FPGAs


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10.1109/iccad45719.2019.8942075

elfPlace: Electrostatics-based Placement for Large-Scale Heterogeneous FPGAs


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10.1109/FPL.2019.00059

Specializing FGPU for Persistent Deep Learning


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10.1145/3337801.3337811

Performance Evaluation of Tsunami Simulation Exploiting Temporal Parallelism on FPGAs using OpenCL


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10.1109/ASAP.2019.00-15

A Virtual Image Accelerator for Graph Cuts Inference on FPGA


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10.1145/3289602.3293988

XFER: A Novel Design to Achieve Super-Linear Performance on Multiple FPGAs for Real-Time AI


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10.1007/978-3-030-38085-4_46

Design of a Real-Time DSP Engine on RF-SoC FPGA for 5G Networks


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10.1007/s00778-019-00581-w

In-memory database acceleration on FPGAs: a survey


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10.1109/ISCAS.2019.8702721

A New Pay-Per-Use Scheme for the Protection of FPGA IP


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10.14311/ap.2019.59.0518

MODEL-BASED SECURITY ANALYSIS OF FPGA DESIGNS THROUGH REINFORCEMENT LEARNING


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10.1145/3289602.3294000

HOTMeTaL: Hardware Optimization Tool for Memory Table and Logic Conversion


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10.1109/SPL.2019.8714446

Design for Portability of Reconfigurable Virtual Instrumentation


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10.23919/DATE.2019.8714724

Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis


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10.1109/FCCM.2019.00069

Improved Techniques for Sensing Intra-Device Side Channel Leakage


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